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141 tm 80c86 cmos 16-bit microprocessor features ? compatible with nmos 8086 ? completely static cmos design - dc . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8mhz (80c86-2) ? low power operation - lccsb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 a max - iccop . . . . . . . . . . . . . . . . . . . . . . . . . 10ma/mhz typ ? 1mbyte of direct memory addressing capability ? 24 operand addressing modes ? bit, byte, word and block move operations ? 8-bit and 16-bit sign ed/unsigned arithmetic - binary, or decimal - multiply and divide ? wide operating temperature range - c80c86 . . . . . . . . . . . . . . . . . . . . . . . . . . 0c to +70c - m80c86 . . . . . . . . . . . . . . . . . . . . . . . .-55c to +125c description the intersil 80c86 high performance 16-bit cmos cpu is manufactured using a self-a ligned silicon gate cmos pro- cess (scaled saji iv). two mode s of operation, minimum for small systems and maximum for larger applications such as multiprocessing, allow user configuration to achieve the highest performance level. full ttl compatibility (with the exception of clock) and industry standard operation allow use of existing nmos 8086 hardware and software designs. ordering information package temp. range ( c) 8mhz part marking pkg. no. pdip 0 to +70 cp80c86-2 cp80c86-2 e40.6 0 to +70 cp80c86-2z cp80c86-2z e40.6 cerdip -55 to +125 md80c86-2/b md80c86-2/b f40.6 smd# -55 to +125 8405202qa 8405202qa f40.6 pinouts 80c86 (dip) top view 80c86 (plcc, clcc) top view 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 gnd ad14 ad13 ad12 ad11 ad10 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 nmi intr clk gnd 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 v cc ad15 a16/s3 a17/s4 a18/s5 a19/s6 bhe /s7 mn/mx rd rq /gt0 rq /gt1 lock s2 s1 s0 qs0 qs1 test ready reset (inta) ( ale) (den) ( dt/r)) ( m/io) (wr) (hlda) (hold) max (min) 14 13 12 11 10 9 8 7 17 16 15 2 5 30 35 39 38 37 36 33 34 32 31 29 4 6 3 1 40 41 42 43 44 28 27 26 25 24 23 22 21 20 19 18 a19/s6 bhe /s7 mn/mx rd hold hlda wr m/io dt/r den nc nc a19/s6 bhe /s7 mn/mx rd rq /gt0 rq /gt1 lock s2 s1 s0 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 ad10 ad10 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 ad12 ad13 ad14 gnd nc v cc ad15 a16/s3 a17/s4 a18/s5 ad11 ad11 ad12 ad13 ad14 gnd nc v cc ad15 a16/s3 a17/s4 a18/s5 nmi intr clk gnd nc reset ready test qs1 qs0 nc nc nmi intr clk gnd nc reset ready test inta ale max mode 80c86 min mode 80c86 max mode 80c86 min mode 80c86 august 22, 2006 fn2957.2 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a trademark of intersil americas inc. copyright ? intersil americas inc. 2002. all rights reserved
142 functional diagram register file execution unit control and timing instruction queue 6-byte flags 16-bit alu bus interface unit 16 4 qs0, qs1 s2 , s1 , s0 2 4 3 gnd v cc clk reset ready bus interface unit relocation register file 3 a19/s6 a16/s3 inta , rd , wr dt/r , den , ale, m/io bhe /s7 2 segment registers and instruction pointer (5 words) data pointer and index regs (8 words) test intr nmi hlda hold rq /gt 0 , 1 lock mn/mx 3 es cs ss ds ip ah bh ch dh al bl cl dl sp bp si di arithmetic/ logic unit b-bus c-bus execution unit interface unit bus queue instruction stream byte execution unit control system flags memory interface a-bus ad15-ad0 80c86
143 pin description the following pin function descriptions ar e for 80c86 systems in either minimum or ma ximum mode. the ?local bus? in these descr iption is the direct multiplexed bus interface connection to the 80c86 (without regard to additional bus buffers). symbol pin number type description ad15-ad0 2-16, 39 i/o address data bus: these lines consti tute the time multiplex ed memory/lo addr ess (t1) and data (t2, t3, tw, t4) bus. a0 is analogous to bhe for the lower byte of the data bus, pins d7- d0. it is low during ti when a byte is to be tr ansferred on the lower portion of the bus in memory or i/o operations. eight-bit oriented devices tied to the lower half would normally use a0 to con- dition chip select functions (see bhe ). these lines are active high and are held at high imped- ance to the last valid logic level during inte rrupt acknowledge and loca l bus ?hold acknowledge? or ?grant sequence?. a19/s6 a18/s5 a17/s4 a16/s3 35-38 o address/status: during t1, these are the four most significant address lines for memory op- erations. during i/o operations these lines are low. during me mory and i/o operations, status information is available on these lines during t2, t3, tw, t4. s6 is always low. the status of the interrupt enable flag bit (s5) is updated at the beginning of each clock cycle. s4 and s3 are encoded as shown. this information indicates which segment regist er is presently being used for data accessing. these lines are held at high impedance to the last valid logic level during local bus ?hold ac- knowledge? or ?grant sequence?. bhe /s7 34 o bus high enable/status: during t1 the bus high enable signal (bhe ) should be used to enable data onto the most significant half of the data bus, pins d15-d8. eight bit oriented devices tied to the upper half of the bus would normally use bhe to condition chip select functions. bhe is low during t1 for read, write, and interrupt acknowledge cycles when a byte is to be trans- ferred on the high portion of the bus. the s7 stat us information is available during t2, t3 and t4. the signal is active low, an d is held at high impedance to t he last valid logic level during interrupt acknowledge and local bus ?hold acknow ledge? or ?grant sequence?, it is low during t1 for the first interrupt acknowledge cycle. rd 32 o read: read strobe indicates that the processor is performing a memory or i/o read cycle, de- pending on the state of the m/io or s2 pin. this signal is used to read devices which reside on the 80c86 local bus. rd is active low during t2, t3 and tw of any read cycle, and is guaran- teed to remain high in t2 until the 80c86 local bus has floated. this line is held at a high impedance logic one state during ?hold acknowledge? or ?grand se- quence?. ready 22 i ready: is the acknowledgment from the addr essed memory or i/o device that will complete the data transfer. the rdy signal from memory or i/o is synchronized by the 82c84a clock gen- erator to form ready. this signal is active high. the 80c86 ready input is not synchronized. correct operation is not guaranteed if the setup and hold times are not met. s4 s3 characteristics 0 0 alternate data 01stack 1 0 code or none 11data bhe a0 characteristics 0 0 whole word 0 1 upper byte from/to odd address 1 0 lower byte from/to even address 1 1 none 80c86
144 intr 18 i interrupt request: is a level triggered input which is sampled during the last clock cycle of each instruction to determine if the proc essor should enter into an interrupt acknowledge op- eration. a subroutine is vectored to via an inte rrupt vector lookup table located in system mem- ory. it can be internally masked by software resetting the interrupt enable bit. lntr is internally synchronized. this signal is active high. test 23 i test: input is examined by the ?wait? instruction. if the test input is low execution continues, otherwise the processor waits in an ?idle? state. this input is synchr onized internally during each clock cycle on the leading edge of clk. nmi 17 i non-maskable interrupt: is an edge triggered input which causes a type 2 interrupt. a subroutine is vectored to via an interrupt vector lookup table located in system memory. nmi is not maskable internally by softwa re. a transition from low to high initiates the interrupt at the end of the current instruction. this input is inter nally synchronized. reset 21 i reset: causes the processor to immediately te rminate its present activity. the signal must tran- sition low to high and remain active high for at least four clock cycles . it restarts execution, as described in the instruction set description, when reset returns low. reset is internally synchronized. clk 19 i clock: provides the basic timing for the proc essor and bus controller. it is asymmetric with a 33% duty cycle to provide optimized internal timing. vcc 40 vcc: +5v power supply pin. a 0.1 f capacitor between pins 20 and 40 is recommended for de- coupling. gnd 1, 20 gnd: ground. note: both must be connected. a 0.1 f capacitor between pins 1 and 20 is rec- ommended for decoupling. mn/mx 33 i minimum/maximum: indicates what mode the processor is to operate in. the two modes are discussed in the following sections. minimum mode system the following pin function descriptions are for the 80c86 in minimum mode (i.e., mn/mx = v cc ). only the pin functions which are unique to minimum mode are described; all other pin functions are as described below. symbol pin number type description m/io 28 o status line: logically equivalent to s2 in the maximum mode. it is used to distinguish a mem- ory access from an i/o access. m/lo becomes valid in the t4 preceding a bus cycle and remains valid until the final t4 of the cycle (m = high, i/o = low). m/lo is held to a high impedance logic one during local bus ?hold acknowledge?. wr 29 o write: indicates that the processor is perform ing a write memory or write i/o cycle, depending on the state of the m/io signal. wr is active for t2, t3 and tw of any write cycle. it is active low, and is held to high impedance logic one during local bus ?hold acknowledge?. inta 24 o interrupt acknowledge: is used as a read strobe for interrupt acknowledge cycles. it is active low during t2, t3 and tw of each interrupt acknowledge cycle. note that inta is never floated. ale 25 o address latch enable: is provided by the processor to latch the address into the 82c82/82c83 address latch. it is a high pulse acti ve during clock low of t1 of any bus cycle. note that ale is never floated. pin description (continued) the following pin function descriptions ar e for 80c86 systems in either minimum or ma ximum mode. the ?local bus? in these descr iption is the direct multiplexed bus interface connection to the 80c86 (without regard to additional bus buffers). symbol pin number type description 80c86
145 dt/r 27 o data transmit/receive: is needed in a mini mum system that desires to use a data bus transceiver. it is used to control the directi on of data flow through the transceiver. logically, dt/r is equivalent to s1 in maximum mode, and its timing is the same as for m/io (t = high, r = low). dt/r is held to a high impedance logic one du ring local bus ?hold acknowledge?. den 26 o data enable: provided as an output enable for a bus transceiver in a minimum system which uses the transceiver. den is active low during each memory and i/o access and for inta cy- cles. for a read or inta cycle it is active from the middle of t2 until the middle of t4, while for a write cycle it is active from the begi nning of t2 until the middle of t4. den is held to a high impedance logic one during lo cal bus ?hold acknowledge?. hold hlda 31, 30 i o hold: indicates that another master is reques ting a local bus ?hold?. to be an acknowledged, hold must be active high. the processor receiv ing the ?hold? will issue a ?hold acknowledge? (hlda) in the middle of a t4 or ti clock cy cle. simultaneously with the issuance of hlda, the processor will float the local bus and control li nes. after hold is detected as being low, the processor will lower hlda, and when the processo r needs to run another cycle, it will again drive the local bus and control lines. hold is not an asynchronous input. external syn chronization should be provided if the system cannot otherwise guarantee the setup time. maximum mode system the following pin function descri ptions are for the 80c86 system in maximum mode (i.e., mn/mx - gnd). only the pi n functions which are unique to maximum mode are described below. symbol pin number type description s0 s1 s2 26 27 28 o o o status: is active during t4, t1 and t2 and is re turned to the passive state (1, 1, 1) during t3 or during tw when ready is high. this status is used by the 82c88 bus controller to generate all memory and i/o access c ontrol signals. any change by s2 , s1 or s0 during t4 is used to indicate the beginning of a bus cycle, and the return to the passive state in t3 or tw is used to indicate the end of a bus cycle. these signals are held at a high impedance logic one state during ?grant sequence?. minimum mode system (continued) the following pin function descriptions are for the 80c86 in minimum mode (i.e., mn/mx = v cc ). only the pin functions which are unique to minimum mode are described; all other pin functions are as described below. symbol pin number type description s2 s1 s0 characteristics 0 0 0 interrupt acknowledge 0 0 1 read i/o port 0 1 0 write i/o port 011halt 1 0 0 code access 1 0 1 read memory 1 1 0 write memory 111passive 80c86
146 rq /gt0 rq /gt1 31, 30 i/o request/grant: pins are used by other loca l bus masters to force the processor to release the local bus at the end of the processor?s curre nt bus cycle. each pi n is bidirectional with rq /gto having higher priority than rq /gt 1. rq /gt has an internal pull-up bus hold device so it may be left unconnected. the request/grant sequence is as follows (see rq /gt sequence timing) 1. a pulse of 1 clk wide from another local bus master indicates a local bus request (?hold?) to the 80c86 (pulse 1). 2. during a t4 or ti clock cycle, a pulse 1 cl k wide from the 80c86 to the requesting master (pulse 2) indicates that the 80c86 has allo wed the local bus to float and that it will enter the ?grant sequence? state at the next clk. the cpu?s bus interface uni t is disconnected logi- cally from the local bus during ?grant sequence?. 3. a pulse 1 clk wide from the requesting master indicates to the 80c86 (pulse 3) that the ?hold? request is about to end and that the 80c 86 can reclaim the local bus at the next clk. the cpu then enters t4 (or ti if no bus cycles pending). each master-master exchange of the local bus is a sequence of 3 pulses. there must be one idle clk cycle after each bus ex change. pulses are active low. if the request is made while the cpu is performing a memory cycle, it will release the local bus during t4 of the cycle when al l the following conditions are met: 1. request occurs on or before t2. 2. current cycle is not the low byte of a word (on an odd address). 3. current cycle is not the first ackn owledge of an interrupt acknowledge sequence. 4. a locked instruction is not currently executing. if the local bus is idle when the request is made the two possible events will follow: 1. local bus will be released during the next cycle. 2. a memory cycle will start within three clocks. now the four rules for a currently active memory cycle apply with condition number 1 already satisfied. lock 29 o lock: output indicates that other system bus masters are not to gain control of the system bus while lock is active low. the lock signal is activated by the ?lock? prefix instruction and remains active until the completion of the next inst ruction. this signal is active low, and is held at a high impedance logic one state during ?grant sequence?. in max mode, lock is automat- ically generated during t2 of the first inta cycle and removed during t2 of the second inta cycle. qs1, qso 24, 25 o queue status: the queue status is valid during the clk cycle after which the queue opera- tion is performed. qs1 and qs0 provide status to allow external tracking of the internal 80c86 instruction queue. note that qs1, qs0 never become high impedance. maximum mode system (continued) the following pin function descri ptions are for the 80c86 system in maximum mode (i.e., mn/mx - gnd). only the pi n functions which are unique to maximum mode are described below. symbol pin number type description qsi qso 0 0 no operation 0 1 first byte of op code from queue 1 0 empty the queue 1 1 subsequent byte from queue 80c86
147 functional description static operation all 80c86 circuitry is of static design. internal registers, counters and latches are static and require no refresh as with dynamic circuit design. th is eliminates the minimum operating frequency restriction placed on other microproces- sors. the cmos 80c86 can operate from dc to the speci- fied upper frequency limit. the processor clock may be stopped in either state (high/low) and held there indefi- nitely. this type of operation is especially useful for system debug or power critical applications. the 80c86 can be single stepped using only the cpu clock. this state can be maintained as long as is necessary. single step clock operation allows simp le interface circuitry to pro- vide critical information for bringing up your system. static design also allows very low frequency operation (down to dc). in a power critical situation, this can provide extremely low power operation since 80c86 power dissipa- tion is directly related to operating frequency. as the system frequency is reduced, so is t he operating power until, ulti- mately, at a dc input frequency, the 80c86 power require- ment is the standby current, (500 a maximum). internal architecture the internal functions of the 80c 86 processor are partitioned logically into two processing units. the first is the bus inter- face unit (blu) and the second is the execution unit (eu) as shown in the cpu functional diagram. these units can interact directly, but for the most part perform as separate asynchronous operational processors. the bus interface unit provides the functions related to instruction fetching and queuing, operand fetch and store, and address relocation. this unit also provides the basic bus control. the overlap of instruction pre-fetchi ng provided by this unit serves to increase processor perf ormance through improved bus bandwidth utilization. up to 6 bytes of the instruction stream can be queued while waiting for decoding and execution. the instruction stream queuing mechanism allows the biu to keep the memory utilized very efficiently. whenever there is space for at least 2 bytes in the queue, the blu will attempt a word fetch memory cycle. this greatly reduces ?dead-time? on the memory bus. the queue ac ts as a first-in-first-out (fifo) buffer, from which the eu extracts instruction bytes as required. if the queue is empty (following a branch instruction, for example), the first byte into the queue imme- diately becomes available to the eu. the execution unit receives pre- fetched instructions from the blu queue and provides un-relocated operand addresses to the blu. memory operands are passed through the biu for pro- cessing by the eu, which passes results to the biu for storage. memory organization the processor provides a 20-bit address to memory, which locates the byte being referenced. the memory is organized as a linear array of up to 1 million bytes, addressed as 00000(h) to fffff(h). the memory is logically divided into code, data, extra and stack segments of up to 64k bytes each, with each segment falling on 16-byte boundaries. (see figure 1). all memory references are made relative to base addresses contained in high speed segm ent registers. the segment types were chosen based on the addressing needs of pro- grams. the segment register to be selected is automatically chosen according to the specific rules of table 1. all informa- tion in one segment type share the same logical attributes (e.g. code or data). by structuring memory into re-locatable areas of similar characteristic s and by automatically select- ing segment registers, programs are shorter, faster and more structured. (see table 1). word (16-bit) operands can be located on even or odd address boundaries and are thus, not constrained to even boundaries as is the case in many 16-bit computers. for address and data operands, the least significant byte of the word is stored in the lower valued address location and the most significant byte in the next higher address location. the biu automatically performs the proper number of memory table 1. type of memory reference default segment base alternate segment base offset instruction fetch cs none ip stack operation ss none sp variable (except following) ds cs, es, ss effective address string source ds cs, es, ss si string destination es none di bp used as base register ss cs, ds, es effective address segment register file cs ss ds es 64k-bit + offset fffffh code segment xxxxoh stack segment data segment extra segment 00000h figure 1. 80c86 memory organization 80c86
148 accesses; one, if the word operand is on an even byte boundary and two, if it is on an odd byte boundary. except for the performance penalty , this double access is transpar- ent to the software. the performance penalty does not occur for instruction fetches; only word operands. physically, the memory is organized as a high bank (d15- d8) and a low bank (d7-d0) of 512k bytes addressed in par- allel by the processor?s address lines. byte data with even addresses is transferred on the d7-d0 bus lines, while odd addressed by te data (a0 high) is trans- ferred on the d15-d8 bus lines. the processor provides two enable signals, bhe and a 0 , to selectively allow reading from or writing into either an odd byte location, even byte location, or both. the instru ction stream is fetched from memory as words and is addressed internally by the proces- sor at the byte level as necessary. in referencing word data, the blu requires one or two memory cycles depending on whether the starting byte of the word is on an even or odd address, respectively. consequently, in ref- erencing word operands perform ance can be optimized by locating data on even address boundaries. this is an espe- cially useful technique for using the stack, since odd address references to the stack may adversely affect the context switching time for interrupt processing or task multiplexing. certain locations in memory are reserved for specific cpu operations (see figure 2). locations from address ffff0h through fffffh are reserved for operations including a jump to the initial program loading routine. following reset, the cpu will always begin execut ion at location ffff0h where the jump must be located. locations 00000h through 003ffh are reserved for interrupt operations. each of the 256 possible interrupt service routines is accessed thru its own pair of 16- bit pointers (segment address pointer and offset address pointer). the first pointer, used as the offset address, is loaded into the lp and the second pointer, which designates the base address is loaded into the cs. at this point program control is transferred to the inte rrupt routine. the pointer ele- ments are assumed to have been stored at the respective places in reserved memory prior to occurrence of interrupts. minimum and maximum operation modes the requirements for supporting minimum and maximum 80c86 systems are sufficiently different that they cannot be met efficiently using 40 uniquely defined pins. consequently, the 80c86 is equipped with a strap pin (mn/mx ) which defines the system configuration. the definition of a certain subset of the pins changes, dependent on the condition of the strap pin. when the mn/mx pin is strapped to gnd, the 80c86 defines pins 24 through 31 and 34 in maximum mode. when the mn/mx pin is strapped to v cc , the 80c86 gener- ates bus control signals itself on pins 24 through 31 and 34. the minimum mode 80c86 can be used with either a multi- plexed or demultiplexed bus. this architecture provides the 80c86 processing power in a highly integrated form. the demultiplexed mode requires two 82c82 latches (for 64k addressability) or three 82c82 la tches (for a full megabyte of addressing). an 82c86 or 82c87 transceiver can also be used if data bus buffering is required. (see figure 6a.) the 80c86 provides den and dt/r to control the transceiver, and ale to latch the addresses. this configuration of the minimum mode provides the standard dem ultiplexed bus structure with heavy bus buffering and relaxed bus timing requirements. the maximum mode employs the 82c88 bus controller (see figure 6b). the 82c88 decodes status lines s0 , s1 and s2 , and provides the system with all bus control signals. moving the bus control to t he 82c88 provides better source and sink current capability to the control lines, and frees the 80c86 pins for extended large system features. hardware lock, queue status, and two request/grant interfaces are pro- vided by the 80c86 in maximum mode. these features allow coprocessors in local bus and remote bus configurations. bus operation the 80c86 has a combined address and data bus com- monly referred to as a time multiplexed bus. this technique provides the most efficient us e of pins on the processor while permitting the use of a standard 40 lead package. this ?local bus? can be buffered directly and used throughout the system with address latching provided on memory and i/o modules. in addition, the bus can also be demultiplexed at the processor with a single set of 82c82 address latches if a standard non-multiplexed bu s is desired for the system. each processor bus cycle consists of at least four clk cycles. these are referred to as t1, t2, t3 and t4 (see fig- ure 3). the address is emitted from the processor during t1 and data transfer occurs on the bus during t3 and t4. t2 is used primarily for changing the direction of the bus during read operations. in the event that a ?not ready? indication is given by the addressed device, ?wait? states (tw) are inserted between t3 and t4. each inserted wait state is the same duration as a clk cycle. periods can occur between 80c86 driven bus cycles. these are referred to as idle? states (t i ) or inactive clk cycles. the processor uses these cycles for internal housek eeping and processing. during t1 of any bus cycle, the ale (address latch enable) signal is emitted (by either the processor or the 82c88 bus controller, depending on the mn/mx strap). at the trailing edge of this pulse, a valid address and certain status infor- mation for the cycl e may be latched. status bits s0 , s1 and s2 are used by the bus controller, in maximum mode, to identify the type of bus transaction according to table 2. table 2. s2 s1 s0 characteristics 0 0 0 interrupt 0 0 1 read i/o 010write i/o 011halt 1 0 0 instruction fetch 1 0 1 read data from memory 1 1 0 write data to memory 1 1 1 passive (no bus cycle) 80c86
149 status bits s3 through s7 are time multiplexed with high order address bits and the bhe signal, and are therefore valid during t2 through t4. s3 and s4 indicate which seg- ment register (see instruction set description) was used for this bus cycle in forming the address, according to table 3. s5 is a reflection of the psw interrupt enable bit. s3 is always zero and s7 is a spare status bit. i/o addressing in the 80c86, i/o operations can address up to a maximum of 64k i/o byte registers or 32k i/o word registers. the i/o address appears in the same format as the memory address on bus lines a15-a0. the address lines a19-a16 are zero in i/o operations. the variable i/o instructions which use regis- ter dx as a pointer have full address capability while the direct i/o instructions directly address one or two of the 256 i/o byte locations in page 0 of the i/o address space. i/o ports are addressed in the same manner as memory loca- tions. even addressed bytes are transferred on the d7-d0 bus lines and odd addressed bytes on d15-d8. care must be taken to ensure that each register with in an 8-bit peripheral located on the lower portion of the bus be addressed as even. table 3. s4 s3 characteristics 0 0 alternate data (extra segment) 01stack 1 0 code or none 11data type 225 pointer (available) reset bootstrap program jump type 33 pointer (available) type 32 pointer (available) type 31 pointer (available) type 5 pointer (reserved) type 4 pointer overflow type 3 pointer 1 byte int instruction type 2 pointer non maskable type 1 pointer single step type 0 pointer divide error 16 bits cs base address ip offset 014h 010h 00ch 008h 004h 000h 07fh 080h 084h ffff0h fffffh 3ffh 3fch available interrupt pointers (224) dedicated interrupt pointers (5) reserved interrupt pointers (27) figure 2. reserved memory locations 80c86
150 (4 + nwait) = tcy t1 t2 t3 t4 twait t1 t2 t3 t4 twait (4 + nwait) = tcy goes inactive in the state just prior to t 4 bhe , a19-a16 s7-s3 a15-a0 d15-d0 valid a15-a0 data out (d15-d0) ready ready wait wait memory access time addr/ status clk ale s 2-s 0 addr/data rd , inta ready dt/r den wr bhe a19-a16 s7-s3 bus reserved for data in figure 3. basic system timing 80c86
151 external interface processor reset an d initialization processor initialization or start up is accomplished with activa- tion (high) of the reset pin. the 80c86 reset is required to be high for greater than 4 clk cyc les. the 80c86 will termi- nate operations on the high-going edge of reset and will remain dormant as long as reset is high. the low-going transition of reset triggers an internal reset sequence for approximately 7 clock cycles. af ter this interval, the 80c86 operates normally beginning with the instruction in absolute location ffff0h. (see figure 2 ). the reset input is internally synchronized to the processor clock. at initialization, the high- to-low transition of reset mu st occur no sooner than 50 s (or 4 clk cycles, whichever is gr eater) after powe r-up, to allow complete initializat ion of the 80c86. nml will not be recognized prior to the second clk cycle follow- ing the end of reset. if nml is asserted sooner than nine clock cycles after the end of reset, the processor may execute one instruction before respon ding to the interrupt. bus hold circuitry to avoid high current conditions caused by floating inputs to cmos devices and to eliminate need for pull-up/down resistors, ?bus-hold? circuitry has been used on the 80c86 pins 2-16, 26- 32 and 34-39. (see figure 4a and figure 4b). these circuits will maintain the last valid logi c state if no driving source is present (i.e., an unconnected pi n or a driving source which goes to a high impedance state). to overdrive the ?bus hold? circuits, an external driver must be capable of supplying approximately 400 a minimum sink or source current at valid input voltage levels. since this ?bus hold? circ uitry is active and not a ?resis- tive? type element, the associated power supply current is negli- gible and power dissipation is significantly reduced when compared to the use of passive pull-up resistors. interrupt operations interrupt operations fall into two classes: software or hard- ware initiated. the software initiated interrupts and software aspects of hardware interrupts are specified in the instruc- tion set description. hardware interrupts can be classified as non-maskable or maskable. interrupts result in a transfer of control to a new program loca- tion. a 256-element table containing address pointers to the interrupt service program locations resides in absolute loca- tions 0 through 3ffh, which are reserved for this purpose. each element in the table is 4 bytes in size and corresponds to an interrupt ?type?. an inte rrupting device supplies an 8-bit type number during the interrupt acknowledge sequence, which is used to ?vector? through the appropriate element to the new interrupt service program location. all flags and both the code segment and instruction pointer register are saved as part of the lnta sequence. these are restored upon exe- cution of an interrupt return (iret) instruction. non-maskable interrupt (nmi) the processor provides a single non-maskable interrupt pin (nmi) which has higher priority than the maskable interrupt request pin (intr). a typical use would be to activate a power failure routine. the nmi is edge-triggered on a low- to-high transition. the activation of this pin causes a type 2 interrupt. nml is required to have a duration in the high state of greater than two clk cycles, but is not required to be syn- chronized to the clock. any positive transition of nmi is latched on-chip and will be serviced at the end of the current instruction or between whole moves of a block-type instruc- tion. worst case response to nmi would be for multiply, divide, and variable shift instru ctions. there is no specifica- tion on the occurrence of t he low-going edge; it may occur before, during or after the servicing of nmi. another positive edge triggers another response if it occurs after the start of the nmi procedure. the signal must be free of logical spikes in general and be free of bounces on the low-going edge to avoid triggering extraneous responses. maskable interrupt (intr) the 80c86 provides a single interrupt request input (lntr) which can be masked internally by software with the reset- ting of the interrupt enable flag (if) status bit. the interrupt request signal is level triggered. it is internally synchronized during each clock cycle on the high-going edge of clk. to be responded to, lntr must be present (high) during the clock period preceding the end of the current instruction or the end of a whole move for a block type instruction. lntr may be removed anytime after the falling edge of the first inta signal. during the interrupt response sequence further interrupts are disabled. the enable bit is reset as part of the response to any inte rrupt (lntr, nmi, so ftware interrupt or single-step), although the flag s register which is automati- cally pushed onto the stack reflects the state of the proces- sor prior to the interrupt. until the old flags register is restored, the enable bit will be ze ro unless specifically set by an instruction. figure 4a. bus hold circuitry pin 2-16, 34-39 figure 4b. bus hold circuitry pin 26-32 output driver input buffer input protection circuitry bond pad external pin output driver input buffer input protection circuitry external pin p v cc bond pad 80c86
152 during the response sequence (figure 5) the processor exe- cutes two successive (back-to- back) interrupt acknowledge cycles. the 80c86 emits the lock signal (max mode only) from t2 of the first bus cycle until t2 of the second. a local bus ?hold? request will not be honored until the end of the second bus cycle. in the second bus cycle, a byte is supplied to the 80c86 by the 82c59a interrupt controller, which iden- tifies the source (type) of the interrupt. this by te is multiplied by four and used as a pointer into the interrupt vector lookup table. an intr signal left high will be continually responded to within the limitations of the enable bit and sample period. the interrupt return instruction includes a flags pop which returns the status of the original interrupt enable bit when it restores the flags. halt when a software ?halt? instruction is executed the proces- sor indicates that it is entering the ?halt? state in one of two ways depending upon which mode is strapped. in minimum mode, the processor issues one ale with no qualifying bus control signals. in maximum mode the processor issues appropriate halt status on s2 , s1 , s0 and the 82c88 bus controller issues one ale. the 80c86 will not leave the ?halt? state when a local bus ?hold? is entered while in ?halt?. in this case, the proc essor reissues the halt indi- cator at the end of the local bus hold. an nmi or interrupt request (when interrupts enabled) or reset will force the 80c86 out of the ?halt? state. read/modify/write (semaphore) operations via lock the lock status information is provided by the processor when consecutive bus cycles are required during the execution of an instruction. this gives t he processor the capability of per- forming read/modify/write operat ions on memory (via the exchange register with memory instruction, for example) with- out another system bus master receiving intervening memory cycles. this is useful in multip rocessor system configurations to accomplish ?test and set lock? operations. the lock signal is activated (forced low) in the clock cycle following decoding of the software ?lock? prefix instru ction. it is deactivated at the end of the last bus cycle of the in struction following the ?lock? prefix instruction. while lock is active a request on a rq/gt pin will be recorded and then hono red at the end of the lock. external synchronization via test as an alternative to interrupts, the 80c86 provides a single software-testable input pin (test ). this input is utilized by executing a wait instruction. the single wait instruction is repeatedly executed until the test input goes active (low). the execution of wa it does not consume bus cycles once the queue is full. if a local bus request occurs during wait execution, the 80c86 three-states all output drivers while inputs and i/o pins are held at valid logic levels by internal bus-hold cir- cuits. if interrupts are enabled, the 80c86 will recognize interrupts and process them when it regains control of the bus. the wait instruction is then refetched, and re-exe- cuted. table 4. 80c86 register basic system timing typical system confi gurations for the pr ocessor operating in minimum mode and in maximum mode are shown in figures 6a and 6b, respectively. in minimum mode, the mn/mx pin is strapped to vcc and the pr ocessor emits bus control sig- nals (e.g. rd , wr , etc.) directly. in maximum mode, the mn/mx pin is strapped to gnd and the processor emits coded status information which the 82c88 bus controller uses to generate multibus compatible bus control signals. figure 3 shows the signal timing relationships. system timing - minimum system the read cycle begins in t1 with the assertion of the address latch enable (ale) signal. the trailing (low-going) edge of this signal is used to latch the address information, which is valid on the address/data bus (ad0-ad15) at this time, into the 82c82/82c83 latch. the bhe and a0 signals address the low, high or both by tes. from t1 to t4 the m/lo signal indicates a memory or i/o operation. at t2, the address is removed from the address/data bus and the bus ale lock inta ad0- float type ad15 t1 t2 t3 t4 ti t1 t2 t3 t4 vector figure 5. interrupt acknowledge sequence ah al bh ch dh bl cl dl sp bp si di ip flags h flags l cs ds ss es ax bx cx dx accumulator base count data stack pointer base pointer source index destination index instruction pointer status flag code segment data segment stack segment extra segment 80c86
153 is held at the last valid logic state by internal bus hold devices. the read control signal is also asserted at t2. the read (rd ) signal causes the addressed device to enable its data bus drivers to the local bus. some time later, valid data will be available on the bus and the addressed device will drive the ready line high . when the processor returns the read signal to a high level, the addressed device will again three-state its bus drivers. if a transceiver (82c86/82c87) is required to buffer the 80c86 local bus, signals dt/r and den are provided by the 80c86. a write cycle also begins with the assertion of ale and the emission of the address. the m/io signal is again asserted to indicate a memory or i/o write operation. in t2, immedi- ately following the address emission, the processor emits the data to be written into the addressed location. this data remains valid until at least the middle of t4. during t2, t3 and tw, the processor asserts the write control signal. the write (wr ) signal becomes active at the beginning of t2 as opposed to the read which is delayed somewhat into t2 to provide time for output drivers to become inactive. the bhe and a0 signals are used to select the proper byte(s) of the memory/lo word to be read or written accord- ing to table 5. i/o ports are addressed in the same manner as memory location. even addressed bytes are transferred on the d7- d0 bus lines and odd address bytes on d15-d8. the basic difference between the interrupt acknowledge cycle and a read cycle is that the interrupt a cknowledge sig- nal (inta ) is asserted in place of the read (rd ) signal and the address bus is held at the last valid logic state by internal bus hold devices. (see figure 4). in the second of two suc- cessive inta cycles a byte of information is read from the data bus (d7-d0) as supplied by the interrupt system logic (i.e., 82c59a priority interrupt controller). this byte identi- fies the source (type) of the in terrupt. it is multiplied by four and used as a pointer into an interrupt vector lookup table, as described earlier. table 5. bhe a0 characteristics 00whole word 0 1 upper byte from/to odd address 1 0 lower byte from/to even address 1 1 none 80c86
154 bus timing - medium size systems for medium complexity systems the mn/mx pin is con- nected to gnd and the 82c88 bus controller is added to the system as well as an 82c82/82c83 latch for latching the system address, and an 82c86/82c87 transceiver to allow for bus loading greater than the 80c86 is capable of han- dling. signals ale, den , and dt/r are generated by the 82c88 instead of the processor in this configuration, although their timing remains relatively the same. the 80c86 status outputs (s2 , s1 and s0 ) provide type-of-cycle information and become 82c88 inputs. this bus cycle infor- mation specifies read (code, data or i/o), write (data or i/o), interrupt acknowledge, or software halt. the 82c88 issues control signals specifying memory read or write, i/o read or write, or interrupt acknowle dge. the 82c88 provides two types of write strobes, normal and advanced, to be applied as required. the normal write strobes have data valid at the leading edge of write. the adv anced write strobes have the same timing as read strobes, and hence, data is not valid at the leading edge of write. the 82c86/82c87 transceiver receives the usual t and oe inputs from the 82c88 dt/r and den signals. the pointer into the interrupt vector table, which is passed during the second inta cycle, can be derived from an 82c59a located on either the local bus or the system bus. if the master 82c59a priority interrupt controller is positioned on the local bus, the 82c86/82c87 transceiver must be dis- abled when reading from the master 82c59a during the interrupt acknowledge sequence and software ?poll?. figure 6a. minimum mode 80c86 typical configuration gnd 82c8a/85 clock bhe a16-a19 ad0-ad15 ale 80c86 cpu dt/r wr rd mn/mx reset ready clk v cc c1 c2 gnd gnd 1 20 40 c1 = c2 = 0.1 f v cc v cc stb oe 82c82 t oe 82c86 transceiver (2) bhe addr data a0 e g hm-6616 cmos prom (2) 2k x 8 2k x 8 cs rd wr cmos 82cxx peripherals hm-6516 cmos ram 2k x 8 w g gnd v cc wait state generator generator res rdy m/io inta den latch 2 or 3 e h e l 2k x 8 addr/data optional for increased data bus drive 80c86
155 figure 6b. maximum mode 80c86 typical configuration absolute maximum ratings thermal information supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0v input, output or i/o voltage . . . . . . . . . . . .gnd -0.5v to v cc +0.5v storage temperature range . . . . . . . . . . . . . . . . . -65 o c to +150 o c junction temperature ceramic packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 o c plastic packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150 o c lead temperature (soldering 10s) . . . . . . . . . . . . . . . . . . . . +300 o c (lead tips only for surface mount packages) esd classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 thermal resistance (typical, note 1) ja ( o c/w) jc ( o c/w) pdip package . . . . . . . . . . . . . . . . . . . 50 n/a plcc package . . . . . . . . . . . . . . . . . . 46 n/a sbdip package. . . . . . . . . . . . . . . . . . 30 6 clcc package . . . . . . . . . . . . . . . . . . 40 6 gate count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9750 gates caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditi ons above those indicated in the operational sections of this specification is not i mplied. note: 1. ja is measured with the component mounted on an evaluation pc board in free air. operating conditions operating supply voltage. . . . . . . . . . . . . . . . . . . . . +4.5v to +5.5v m80c86-2 only. . . . . . . . . . . . . . . . . . . . . . . . +4.75v to +5.25v operating temperature range: c80c86/-2 . . . . . . . . 0 o c to +70 o c i80c86/-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to +85 o c m80c86/-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 o c to +125 o c dc electrical specifications v cc = 5.0v, 10%; t a = 0 o c to +70 o c (c80c86, c80c86-2) v cc = 5.0v, 10%; t a = -40 o c to +85 o c (l80c86, i80c86-2) v cc = 5.0v, 10%; t a = -55 o c to +125 o c (m80c86) v cc = 5.0v, 5%; t a = -55 o c to +125 o c (m80c86-2) symbol parameter min max units test condition v lh logical one input voltage 2.0 2.2 v v c80c86, i80c86 (note 5) m80c86 (note 5) gnd 82c84a/85 clock generator/ bhe a16-a19 ad0-ad15 lock 80c86 cpu s2 s1 s0 mn/mx reset ready clk v cc c1 c2 gnd gnd 1 20 40 c1 = c2 = 0.1 f gnd v cc clk s0 s1 s2 den dt/r ale mrdc mwtc amwc iorc iowc aiowc inta 82c88 bus ctrlr stb oe 82c82 (2 or 3) t oe 82c86 transceiver (2) bhe nc nc addr data a0 e g hm-6616 cmos prom (2) 2k x 8 2k x 8 cs rd wr cmos 82cxx peripherals hm-65162 cmos ram 2k x 8 e h gnd v cc nc addr/data wait state generator e l w g 2k x 8 res rdy 80c86
156 v il logical zero input voltage 0.8 v v ihc clk logical one input voltage v cc -0.8 v v ilc clk logical zero input voltage 0.8 v v oh output high voltage 3.0 v cc -0.4 v v l oh = -2.5ma l oh = -100 a v ol output low voltage 0.4 v l ol = +2.5ma i i input leakage current -1.0 1.0 av in = gnd or v cc dip pins 17-19, 21-23, 33 l bhh input current-bus hold high -40 -400 av in = - 3.0v (note 1) l bhl input current-bus hold low 40 400 av in = - 0.8v (note 2) i o output leakage current - -10.0 av out = gnd (note 4) i ccsb standby power supply current - 500 av cc = - 5.5v (note 3) i ccop operating power supply current - 10 ma/mhz freq = max, v in = v cc or gnd, outputs open capacitance t a = 25 o c symbol parameter typical units test conditions c in input capacitance 25 pf freq = 1mhz. all meas urements are referenced to device gnd c out output capacitance 25 pf freq = 1mhz. all m easurements are referenced to device gnd c i/o i/o capacitance 25 pf freq = 1mhz. all meas urements are referenced to device gnd notes: 2. lbhh should be measured after raising v in to v cc and then lowering to 3.0v on the following pins 2-16, 26-32, 34-39. 3. ibhl should be measured after lowering v in to gnd and then raising to 0.8v on the following pins: 2-16, 34-39. 4. lccsb tested during clock high time after halt instruction executed. v in = v cc or gnd, v cc = 5.5v, outputs unloaded. 5. io should be measured by putting the pin in a high impedance state and then driving v out to gnd on the following pins: 26-29 and 32. 6. mn/mx is a strap option and should be held to v cc or gnd. ac electrical specifications v cc = 5.0v 10%; t a = 0 o c to +70 o c (c80c86, c80c86-2) v cc = 5.0v 100%; t a = -40 o c to +85 o c (i80c86, i80c86-2) v cc = 5.0v 100%; t a = -55 o c to +125 o c (m80c86) v cc = 5.0v 5%; t a = -55 o c to +125 o c (m80c86-2) minimum complexity system symbol parameter 80c86 80c86-2 units test conditions min max min max timing requirements (1) tclcl cycle period 200 125 ns (2) tclch clk low time 118 68 ns (3) tchcl clk high time 69 44 ns (4) tch1ch2 clk rise time 10 10 ns from 1.0v to 3.5v (5) tcl2c1 clk fail time 10 10 ns from 3.5v to 1.0v dc electrical specifications v cc = 5.0v, 10%; t a = 0 o c to +70 o c (c80c86, c80c86-2) v cc = 5.0v, 10%; t a = -40 o c to +85 o c (l80c86, i80c86-2) v cc = 5.0v, 10%; t a = -55 o c to +125 o c (m80c86) v cc = 5.0v, 5%; t a = -55 o c to +125 o c (m80c86-2) symbol parameter min max units test condition 80c86
157 (6) tdvcl data in setup time 30 20 ns (7) tcldx1 data in hold time 10 10 ns (8) tr1vcl rdy setup time into 82c84a (notes 7, 8) 35 35 ns (9) tclr1x rdy hold time into 82c84a (notes 7, 8) 00ns (10) tryhch ready setup time into 80c86 118 68 ns (11) tchryx ready hold time into 80c86 30 20 ns (12) trylcl ready inactive to clk (note 9) -8 -8 ns (13) thvch hold setup time 35 20 n s (14) tinvch lntr, nmi, test setup time (note 8) 30 15 ns (15) tilih input rise time (except clk) 15 15 ns from 0.8v to 2.0v (16) tihil input fail time (except clk) 15 15 ns from 2.0v to 0.8v timing responses (17) tclav address valid delay 10 110 10 60 ns c l = 100pf (18) tclax address hold time 10 10 ns c l = 100pf (19) tclaz address float delay tclax 80 tclax 50 ns c l = 100pf (20) tchsz status float delay 80 50 ns c l = 100pf (21) tchsv status active delay 10 110 10 60 ns c l = 100pf (22) tlhll ale width tclch-20 tclch-10 ns c l = 100pf (23) tcllh ale active delay 80 50 ns c l = 100pf (24) tchll ale inactive delay 85 55 ns c l = 100pf (25) tllax address hold time to ale inactive tchcl-10 tchcl-10 ns c l = 100pf (26) tcldv data valid delay 10 110 10 60 ns c l = 100pf (27) tcldx2 data hold time 10 10 ns c l = 100pf (28) twhdx data hold time after wr tclcl-30 tclcl-30 ns c l = 100pf (29) tcvctv control active delay 1 10 110 10 70 ns c l = 100pf (30) tchctv control active delay 2 10 110 10 60 ns c l = 100pf ac electrical specifications v cc = 5.0v 10%; t a = 0 o c to +70 o c (c80c86, c80c86-2) v cc = 5.0v 100%; t a = -40 o c to +85 o c (i80c86, i80c86-2) v cc = 5.0v 100%; t a = -55 o c to +125 o c (m80c86) v cc = 5.0v 5%; t a = -55 o c to +125 o c (m80c86-2) (continued) minimum complexity system symbol parameter 80c86 80c86-2 units test conditions min max min max 80c86
158 (31) tcvctx control inactive delay 10 110 10 70 ns c l = 100pf (32) tazrl address float to read active 0 0 ns c l = 100pf (33) tclrl rd active delay 10 165 10 100 ns c l = 100pf (34) tclrh rd inactive delay 10 150 10 80 ns c l = 100pf (35) trhav rd inactive to next address active tclcl-45 tclcl-40 ns c l = 100pf (36) tclhav hlda valid delay 10 160 10 100 ns c l = 100pf (37) trlrh rd width 2tclcl-75 2tclcl-50 ns c l = 100pf (38) twlwh wr width 2tclcl-60 2tclcl-40 ns c l = 100pf (39) taval address valid to ale low tclch-60 tclch-40 ns c l = 100pf (40) toloh output rise time 20 15 ns from 0.8v to 2.0v (41) tohol output fall time 20 15 ns from 2.0v to 0.8v notes: 7. signal at 82c84a shown for reference only. 8. setup requirement for asynchronous signal only to guarantee recognition at next clk. 9. applies only to t2 state (8ns into t3). ac electrical specifications v cc = 5.0v 10%; t a = 0 o c to +70 o c (c80c86, c80c86-2) v cc = 5.0v 100%; t a = -40 o c to +85 o c (i80c86, i80c86-2) v cc = 5.0v 100%; t a = -55 o c to +125 o c (m80c86) v cc = 5.0v 5%; t a = -55 o c to +125 o c (m80c86-2) (continued) minimum complexity system symbol parameter 80c86 80c86-2 units test conditions min max min max 80c86
159 waveforms figure 7a. bus timing - minimum mode system note: signals at 82c84a are shown for referenc e only. rdy is sampled near the end of t2, t3, tw to determine if tw machine state s are to be inserted. tcvctx (31) (29) tcvctv den dt/ r (30) tchctv tclrl (33) (30) tchctv read cycle (35) (34) tclrh rd data in (7) tcldx1 (10) tryhch ad15-ad0 (24) (17) tclav ready (80c86 input) rdy (82c84a input) see note ale bhe /s7, a19/s6-a16/s3 (17) tclav m/io (30) tchctv clk (82c84a output) (3) tchcl tch1ch2 (4) (2) tclch tchctv (30) (5) tcl2cl1 t1 t2 t3 t w t4 (wr , inta = v oh ) (1) tclcl (26) tcldv (18) tclax bhe , a19-a16 (23) tcllh tlhll (22) tllax (25) tchll taval (39) v il v ih (12) trylcl (11) tchryx (19) tclaz (16) tdvcl ad15-ad0 trhav (32) tazrl trlrh (37) tclr1x (9) tr1vcl (8) s 7 -s 3 80c86
160 figure 7b. bus timing - minimum mode system note: two inta cycles run back-to-back. the 80c86 local addr/data bus is floating during both inta cycles. control signals are shown for the second inta cycle. waveforms (continued) t4 t3 t2 t1 tw tdvcl tcldx1 (7) twhdx tcvctx tchctv (30) tclav tclaz tchctv (31) tcvctx tcvctv (17) (26) (27) (29) tcvctv data out ad15-ad0 invalid address clk (82c84a output) write cycle (rd , inta , dt/r = v oh ) ad15-ad0 den wr inta cycle (see note) (rd , wr = v oh bhe = v ol ) ad15-ad0 dt/r inta den ad15-ad0 software halt - den , rd , wr , inta = v oh dt/r = indeterminate software halt (29) tcvctv pointer tcl2cl1 (5) tw tclav tcldv tclax (18) tcldx2 (29) (28) twlwh (38) (29) tcvctv (19) tcvctx (31) (6) (30) (31) (17) tch1ch2 (4) 80c86
161 ac electrical specifications v cc = 5.0v 10% t a = 0 o c to +70 o c (c80c86, c80c86-2) v cc = 5.0v 10%; t a = -40 o c to +85 o c (i80c86, i80c86-2) v cc = 5.0v 10%; t a = -55 o c to +125 o c (m80c86) v cc = 5.0v 5%; t a = -55 o c to +125 o c (m80c86-2) max mode system (using 82c88 bus controller) timing requirements 80c86 80c86-2 units test conditions symbol parameter min max min max (1) tclcl clk cycle period 200 125 ns (2) tclch clk low time 118 68 ns (3) tchcl clk high time 69 44 ns (4) tch1ch2 clk rise time 10 10 ns from 1.0v to 3.5v (5) tcl2cl1 clk fall time 10 10 ns from 3.5v to 1.0v (6) tdvcl data in setup time 30 20 ns (7) tcldx1 data in hold time 10 10 ns (8) tr1vcl rdy setup time into 82c84a (notes 10, 11) 35 35 ns (9) tclr1x rdy hold time into 82c84a (notes 10, 11) 00ns (10) tryhch ready setup time into 80c86 118 68 ns (11) tchryx ready hold time into 80c86 30 20 ns (12) trylcl ready inactive to clk (note 12) -8 -8 ns (13) tlnvch setup time for recognition (lntr, nml, test ) (note 11) 30 15 ns (14) tgvch rq /gt setup time 30 15 ns (15) tchgx rq hold time into 80c86 (note 13) 40 tchcl+ 10 30 tchcl+ 10 ns (16) tillh input rise time (except clk) 15 15 ns from 0.8v to 2.0v (17) tihil input fall time ( except clk) 15 15 ns from 2.0v to 0.8v timing responses (18) tclml command active delay (note 10) 5 35 5 35 ns c l = 100pf for all 80c86 outputs (in addition to 80c86 self load) (19) tclmh command inactive (note 10) 5 35 5 35 ns c l = 100pf for all 80c86 outputs (in addition to 80c86 self load) (20) tryhsh ready active to status passive (notes 12, 14) 110 65 ns c l = 100pf for all 80c86 outputs (in addition to 80c86 self load) (21) tchsv status active delay 10 110 10 60 ns c l = 100pf for all 80c86 outputs (in addition to 80c86 self load) (22) tclsh status inactive delay (note 14) 10 130 10 70 ns c l = 100pf for all 80c86 outputs (in addition to 80c86 self load) 80c86
162 (23) tclav address valid delay 10 110 10 60 ns c l = 100pf for all 80c86 outputs (in addition to 80c86 self load) (24) tclax address hold time 10 10 ns c l = 100pf for all 80c86 outputs (in addition to 80c86 self load) (25) tclaz address float delay tclax 80 tclax 50 ns c l = 100pf for all 80c86 outputs (in addition to 80c86 self load) (26) tchsz status float delay 80 50 ns c l = 100pf for all 80c86 outputs (in addition to 80c86 self load) (27) tsvlh status valid to ale high (note 10) 20 20 ns c l = 100pf for all 80c86 outputs (in addition to 80c86 self load) (28) tsvmch status valid to mce high (note 10) 30 30 ns c l = 100pf for all 80c86 outputs (in addition to 80c86 self load) (29) tcllh clk low to ale valid (note 10) 20 20 ns c l = 100pf for all 80c86 outputs (in addition to 80c86 self load) (30) tclmch clk low to mce high (note 10) 25 25 ns c l = 100pf for all 80c86 outputs (in addition to 80c86 self load) (31) tchll ale inactive delay (note 10) 4 18 4 18 ns c l = 100pf for all 80c86 outputs (in addition to 80c86 self load) (32) tclmcl mce inactive delay (note 10) 15 15 ns c l = 100pf for all 80c86 outputs (in addition to 80c86 self load) (33) tcldv data valid delay 10 110 10 60 ns c l = 100pf for all 80c86 outputs (in addition to 80c86 self load) (34) tcldx2 data hold time 10 10 ns c l = 100pf for all 80c86 outputs (in addition to 80c86 self load) ac electrical specifications v cc = 5.0v 10% t a = 0 o c to +70 o c (c80c86, c80c86-2) v cc = 5.0v 10%; t a = -40 o c to +85 o c (i80c86, i80c86-2) v cc = 5.0v 10%; t a = -55 o c to +125 o c (m80c86) v cc = 5.0v 5%; t a = -55 o c to +125 o c (m80c86-2) (continued) max mode system (using 82c88 bus controller) timing requirements 80c86 80c86-2 units test conditions symbol parameter min max min max 80c86
163 (35) tcvnv control active delay (note 10) 5 45 5 45 ns c l = 100pf for all 80c86 outputs (in addition to 80c86 self load) (36) tcvnx control inactive delay (note 10) 10 45 10 45 ns c l = 100pf (37) tazrl address float to read active 0 0 ns c l = 100pf (38) tclrl rd active delay 10 165 10 100 ns c l = 100pf (39) tclrh rd inactive delay 10 150 10 80 ns c l = 100pf (40) trhav rd inactive to next address active tclcl -45 tclcl -40 ns c l = 100pf (41) tchdtl direction control active delay (note 10) 50 50 ns c l = 100pf (42) tchdth direction control inactive delay (note 10) 30 30 ns c l = 100pf (43) tclgl gt active delay 10 85 0 50 ns c l = 100pf (44) tclgh gt inactive delay 10 85 0 50 ns c l = 100pf (45) trlrh rd width 2tclc l -75 2tclc l -50 ns c l = 100pf (46) toloh output rise time 20 15 ns from 0.8v to 2.0v (47) tohol output fall time 20 15 ns from 2.0v to 0.8v notes: 10. signal at 82c84a or 82c88 shown for reference only. 11. setup requirement for asynchronous signal only to guarantee recognition at next clk. 12. applies only to t2 state (8ns into t3). 13. the 80c86 actively pulls the rq /gt pin to a logic one on the following clock low time. 14. status lines return to their inactive (logi c one) state after clk goes low and ready goes high. ac electrical specifications v cc = 5.0v 10% t a = 0 o c to +70 o c (c80c86, c80c86-2) v cc = 5.0v 10%; t a = -40 o c to +85 o c (i80c86, i80c86-2) v cc = 5.0v 10%; t a = -55 o c to +125 o c (m80c86) v cc = 5.0v 5%; t a = -55 o c to +125 o c (m80c86-2) (continued) max mode system (using 82c88 bus controller) timing requirements 80c86 80c86-2 units test conditions symbol parameter min max min max 80c86
164 waveforms figure 8a. bus timing - maximum mode (using 82c88) notes: 15. signals at 82c84a or 82c88 are shown for reference only. rdy is sampled near the end of t2, t3, tw to determine if tw machin e states are to be inserted. 16. the issuance of the 82c88 command and control signals (mrdc , mwtc , amwc , iorc , iowc , aiowc , inta , and den ) lags the active high 82c88 cen. 17. status inactive in state just prior to t4. t 1 t 2 t 3 t 4 tclcl tch1ch2 tcl2cl1 t w tchcl (3) (21) tchsv (see note 17) tcldv tclax (23) tclav tclav bhe , a19-a16 tsvlh tcllh tr1vcl tchll tclr1x tclav tdvcl tcldx1 tclax ad15-ad0 data in tryhsh (39) tclrh trhav (41) tchdtl tclrl trlrh tchdth (37) tazrl tclml tclmh (35) tcvnv tcvnx clk qs0, qs1 s 2, s 1, s 0 (except halt) bhe /s7, a19/s6-a16/s3 ale (82c88 output) rdy (82c84 input) note ready 80c86 input) read cycle 82c88 outputs see notes 15, 16 mrdc or iorc den s7-s3 ad15-ad0 rd dt/r tclav (1) (4) (23) tclch (2) tclsh (22) (24) (23) (27) (29) (31) (8) (9) tchryx (11) (20) (12) trylcl (24) tryhch (10) (6) (7) (23) (40) (42) (45) (38) (18) (19) (36) (33) tclaz (25) (5) 80c86
165 figure 8b. bus timing - maximum mode (using 82c88) notes: 18. signals at 82c84a or 82c86 are shown for reference only. 19. the issuance of the 82c88 command and control signals (mrdc , mwtc , amwc , iorc , iowc , aiowc , inta and den ) lags the active high 82c88 cen. 20. status inactive in state just prior to t4. 21. cascade address is valid between first and second inta cycles. 22. two inta cycles run back-to-back. the 80c86 local addr/data bus is floating during both inta cycles. control for pointer address is shown for second inta cycle. waveforms (continued) t1 t2 t3 t4 tw tclsh (see note 20)) tcldx2 tcldv tclax tclmh (18) tclml tchdth (19) tclmh tcvnx tclav tchsv tclsh clk s 2, s 1, s 0 (except halt) write cycle ad 15 -ad 0 den amwc or aiowc mwtc or iowc 82c88 outputs see notes 18, 19 inta cycle ad15-ad0 (see notes 21, 22) ad15-ad0 mce/pden dt/r inta den 82c88 outputs see notes 18, 19 reserved for cascade addr (25) tclaz (30) tclmch tcvnv software halt - rd , mrdc , iorc , mwtc , amwc , iowc , aiowc , inta , s 0, s 1 = voh (18) tclml tclmh (19) tcldx1 (7) (18)tclml pointer invalid address ad15-ad0 s 2 tchdtl tchsv (21) (34) (22) (33) (24) data tcvnx (36) (19) (6) tdvcl tclmcl (32) (41) (42) (35) (36) (23) (21) (22) tclav (23) tcvnv (35) (28) tsvmch 80c86
166 note: the coprocessor may not drive the busses out side the region shown wit hout risking contention. figure 9. request/grant sequence timing (maximum mode only) figure 10. hold/hold acknowledge timing (minimum mode only) note: setup requirements for asynchronous signals only to guar- antee recognition at next clk. figure 11. asynchronous signal recognition figure 12. bus lock signal timing (maximum mode only) waveforms (continued) clk tclgh rq /gt previous grant ad15-ad0 rd , lock bhe/s 7, a19/s0-a16/s3 s 2, s 1, s 0 tclcl any clk cycle >0-clk cycles pulse 2 80c86 tgvch (14) tchgx (15) tclgh (44) pulse 1 coprocessor rq tclaz (25) 80c86 gt pulse 3 coprocessor release (see note) tchsz (26) (1) tclgl (43) coprocessor tchsv (21) (44) clk hold hlda ad15-ad0 bhe /s7, a19/s6-a16/s3 rd , wr , m/io , dt/r , den 80c86 thvch (13) tclhav (36) 1clk 1 or 2 cycles tclaz (19) coprocessor 80c86 tclhav (36) cycle tchsz (20) thvch (13) tchsv (21) nmi intr test clk signal tinvch (see note) (13) any clk cycle clk lock tclav any clk cycle (23) tclav (23) 80c86
167 figure 13. reset timing waveforms (continued) v cc clk reset 50 s 4 clk cycles (7) tcldx1 (6) tdvcl ac test circuit note: includes stay and jig capacitance. ac testing input, output waveform note: ac testing: all input signals (other than clk) must switch between v ilmax -50% v il and v ihmin +20% v ih . clk must switch between 0.4v and v cc .-0.4 input rise and fall times are driven at 1ns/v. output from device under test test point c l (see note) input v ih + 20% v ih v il - 50% v il output v oh v ol 1.5v 1.5v 80c86
168 burn-in circuits md80c86 cerdip notes: v cc = 5.5v 0.5v, gnd = 0v. input voltage limits (except clock): v il (maximum) = 0.4v v ih (minimum) = 2.6v, v ih (clock) = (v cc -0.4v) minimum. v cc/2 is external supply set to 2.7v 10%. v cl is generated on program card (v cc - 0.65v). pins 13 - 16 input sequenced instructio ns from internal hold devices. f 0 = 100khz 10%. node = a 40 s pulse every 2.56ms. components: 1. ri = 10k 5%, 1/4w 2. ro = 1.2k 5%, 1/4w 3. rio = 2.7k 5%, 1/4w 4. rc = 1k 5%, 1/4w 5. c = 0.01 f (minimum) 33 34 35 36 37 38 40 32 31 30 29 24 25 26 27 28 21 22 23 13 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 39 gnd gnd nmi intr clk gnd 1 rio rio rio rio rio rio rio rio rio rio rio rc ri ri v cc/2 v cl v cl v cc/2 gnd v cc/2 v cc/2 ri v cc/2 v cc/2 v cc/2 v cl v cc gnd rio ro ro ro v cc/2 v cc/2 v cc/2 v cc/2 v cc/2 gnd v cl node from program card gnd gnd v cl gnd gnd v cl gnd gnd gnd v cl v cl v cl open open open open gnd gnd f 0 ro ro ro ro ro ro ro ro ro ro a ad14 ad13 ad12 ad11 ad10 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 v cc qs2 test ready reset ad15 ad16 ad17 ad18 ad19 bhe mx rd rq0 rq1 lock s 2 s 1 s 0 qs0 c a 80c86
169 mr80c86 clcc notes: v cc = 5.5v 0.5v, gnd = 0v. input voltage limits (except clock): v il (maximum) = 0.4v v ih (minimum) = 2.6v, v ih (clock) = (v cc -0.4v) minimum. v cc/2 is external supply set to 2.7v 10%. v cl is generated on program card (v cc - 0.65v). pins 13 - 16 input sequenced instructio ns from internal hold devices. f 0 = 100khz 10%. node = a 40 s pulse every 2.56ms. components: 1. ri = 10k 5%, 1/4w 2. ro = 1.2k 5%, 1/4w 3. rio = 2.7k 5%, 1/4w 4. rc = 1k 5%, 1/4w 5. c = 0.01 f (minimum) burn-in circuits (continued) 14 13 12 11 10 9 8 7 17 16 15 2 5 30 35 39 38 37 36 33 34 32 31 29 4 6 3 1 40 41 42 43 44 28 27 26 25 24 23 22 21 20 19 18 rio rio rio rio rio rio rio rio rio rio rio ro ro ro ro ro ro ri ri ro ro ro ro rc ri ri ro ro rio v cc v cl v cc/2 c f 0 (from program card) a gnd a 80c86
170 metallization topology die dimensions: 249.2 x 290.9 x 19 metallization: type: silicon - aluminum thickness: 11k ? 2k ? glassivation: type: nitrox thickness: 10k ? 2k ? worst case current density: 1.5 x 10 5 a/cm 2 metallization mask layout 80c86 ad11 ad12 ad13 ad14 a17/s4 a18/s5 gnd a16/s3 v cc ad15 a19/s6 bhe /s7 mn/mx rd rq /gt0 rq /gt1 lock s 2 s 1 s 0 ad10 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 nmi intr clk gnd reset ready test qs1 qs0 80c86
171 instruction set summary mnemonic and description instruction code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 data transfer mov = move: register/memory to/from register 1 0 0 0 1 0 d w mod reg r/m immediate to register/memory 1 1 0 0 0 1 1 w mod 0 0 0 r/m data data if w 1 immediate to register 1 0 1 1 w reg data data if w 1 memory to accumulator 1 0 1 0 0 0 0 w addr-low addr-high accumulator to memory 1 0 1 0 0 0 1 w addr-low addr-high register/memory to segment register ?? 1 0 0 0 1 1 1 0 mod 0 reg r/m segment register to register/memory 1 0 0 0 1 1 0 0 mod 0 reg r/m push = push: register/memory 1 1 1 1 1 1 1 1 mod 1 1 0 r/m register 0 1 0 1 0 reg segment register 0 0 0 reg 1 1 0 pop = pop: register/memory 1 0 0 0 1 1 1 1 mod 0 0 0 r/m register 0 1 0 1 1 reg segment register 0 0 0 reg 1 1 1 xchg = exchange: register/memory with register 1 0 0 0 0 1 1 w mod reg r/m register with accumulator 1 0 0 1 0 reg in = input from: fixed port 1 1 1 0 0 1 0 w port variable port 1 1 1 0 1 1 0 w out = output to: fixed port 1 1 1 0 0 1 1 w port variable port 1 1 1 0 1 1 1 w xlat = translate byte to al 1 1 0 1 0 1 1 1 lea = load ea to register2 1 0 0 0 1 1 0 1 mod reg r/m lds = load pointer to ds 1 1 0 0 0 1 0 1 mod reg r/m les = load pointer to es 1 1 0 0 0 1 0 0 mod reg r/m lahf = load ah with flags 1 0 0 1 1 1 1 1 sahf = store ah into flags 1 0 0 1 1 1 1 0 pushf = push flags 1 0 0 1 1 1 0 0 popf = pop flags 1 0 0 1 1 1 0 1 arithmetic add = add: register/memory with register to either 0 0 0 0 0 0 d w mod reg r/m immediate to register/memory 1 0 0 0 0 0 s w mod 0 0 0 r/m data data if s:w = 01 immediate to accumulator 0 0 0 0 0 1 0 w data data if w = 1 adc = add with carry: register/memory with register to either 0 0 0 1 0 0 d w mod reg r/m 80c86
172 immediate to register/memory 1 0 0 0 0 0 s w mod 0 1 0 r/m data data if s:w = 01 immediate to accumulator 0 0 0 1 0 1 0 w data data if w = 1 inc = increment: register/memory 1 1 1 1 1 1 1 w mod 0 0 0 r/m register 0 1 0 0 0 reg aaa = ascll adjust for add 0 0 1 1 0 1 1 1 daa = decimal adjust for add 0 0 1 0 0 1 1 1 sub = subtract: register/memory and register to either 0 0 1 0 1 0 d w mod reg r/m immediate from register/memory 1 0 0 0 0 0 s w mod 1 0 1 r/m data data if s:w = 01 immediate from accumulator 0 0 1 0 1 1 0 w data data if w = 1 sbb = subtract with borrow register/memory and register to either 0 0 0 1 1 0 d w mod reg r/m immediate from register/memory 1 0 0 0 0 0 s w mod 0 1 1 r/m data data if s:w = 01 immediate from accumulator 0 0 0 1 1 1 0 w data data if w = 1 dec = decrement: register/memory 1 1 1 1 1 1 1 w mod 0 0 1 r/m register 0 1 0 0 1 reg neg = change sign 1 1 1 1 0 1 1 w mod 0 1 1 r/m cmp = compare: register/memory and register 0 0 1 1 1 0 d w mod reg r/m immediate with register/memory 1 0 0 0 0 0 s w mod 1 1 1 r/m data data if s:w = 01 immediate with accumulator 0 0 1 1 1 1 0 w data data if w = 1 aas = ascll adjust for subtract 0 0 1 1 1 1 1 1 das = decimal adjust for subtract 0 0 1 0 1 1 1 1 mul = multiply (unsigned) 1 1 1 1 0 1 1 w mod 1 0 0 r/m imul = integer multiply (signed) 1 1 1 1 0 1 1 w mod 1 0 1 r/m aam = ascll adjust for multiply 1 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 dlv = divide (unsigned) 1 1 1 1 0 1 1 w mod 1 1 0 r/m idlv = integer divide (signed) 1 1 1 1 0 1 1 w mod 1 1 1 r/m aad = ascli adjust for divide 1 1 0 1 0 1 0 1 0 0 0 0 1 0 1 0 cbw = convert byte to word 1 0 0 1 1 0 0 0 cwd = convert word to double word 1 0 0 1 1 0 0 1 logic not = invert 1 1 1 1 0 1 1 w mod 0 1 0 r/m shl/sal = shift logical/arithmetic left 1 1 0 1 0 0 v w mod 1 0 0 r/m shr = shift logical right 1 1 0 1 0 0 v w mod 1 0 1 r/m sar = shift arithmetic right 1 1 0 1 0 0 v w mod 1 1 1 r/m rol = rotate left 1 1 0 1 0 0 v w mod 0 0 0 r/m ror = rotate right 1 1 0 1 0 0 v w mod 0 0 1 r/m rcl = rotate through carry flag left 1 1 0 1 0 0 v w mod 0 1 0 r/m instruction set summary (continued) mnemonic and description instruction code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 80c86
173 rcr = rotate through carry right 1 1 0 1 0 0 v w mod 0 1 1 r/m and = and: reg./memory and register to either 0 0 1 0 0 0 0 d w mod reg r/m immediate to register/memory 1 0 0 0 0 0 0 w mod 1 0 0 r/m data data if w = 1 immediate to accumulator 0 0 1 0 0 1 0 w data data if w = 1 test = and function to flags, no result: register/memory and register 1 0 0 0 0 1 0 w mod reg r/m immediate data and register/memory 1 1 1 1 0 1 1 w mod 0 0 0 r/m data data if w = 1 immediate data and accumulator 1 0 1 0 1 0 0 w data data if w = 1 or = or: register/memory and register to either 0 0 0 0 1 0 d w mod reg r/m immediate to register/memory 1 0 0 0 0 0 0 w mod 1 0 1 r/m data data if w = 1 immediate to accumulator 0 0 0 0 1 1 0 w data data if w = 1 xor = exclusive or: register/memory and register to either 0 0 1 1 0 0 d w mod reg r/m immediate to register/memory 1 0 0 0 0 0 0 w mod 1 1 0 r/m data data if w = 1 immediate to accumulator 0 0 1 1 0 1 0 w data data if w = 1 string manipulation rep = repeat 1 1 1 1 0 0 1 z movs = move byte/word 1 0 1 0 0 1 0 w cmps = compare byte/word 1 0 1 0 0 1 1 w scas = scan byte/word 1 0 1 0 1 1 1 w lods = load byte/word to al/ax 1 0 1 0 1 1 0 w stos = stor byte/word from al/a 1 0 1 0 1 0 1 w control transfer call = call: direct within segment 1 1 1 0 1 0 0 0 disp-low disp-high indirect within segment 1 1 1 1 1 1 1 1 mod 0 1 0 r/m direct intersegment 1 0 0 1 1 0 1 0 offset-low offset-high seg-low seg-high indirect intersegment 1 1 1 1 1 1 1 1 mod 0 1 1 r/m jmp = unconditional jump: direct within segment 1 1 1 0 1 0 0 1 disp-low disp-high direct within segment-short 1 1 1 0 1 0 1 1 disp indirect within segment 1 1 1 1 1 1 1 1 mod 1 0 0 r/m direct intersegment 1 1 1 0 1 0 1 0 offset-low offset-high seg-low seg-high indirect intersegment 1 1 1 1 1 1 1 1 mod 1 0 1 r/m ret = return from call: within segment 1 1 0 0 0 0 1 1 within seg adding lmmed to sp 1 1 0 0 0 0 1 0 data-low data-high instruction set summary (continued) mnemonic and description instruction code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 80c86
174 intersegment 1 1 0 0 1 0 1 1 intersegment adding immediate to sp 1 1 0 0 1 0 1 0 data-low data-high je/jz = jump on equal/zero 0 1 1 1 0 1 0 0 disp jl/jnge = jump on less/not greater or equal 0 1 1 1 1 1 0 0 disp jle/jng = jump on less or equal/ not greater 0 1 1 1 1 1 1 0 disp jb/jnae = jump on below/not above or equal 0 1 1 1 0 0 1 0 disp jbe/jna = jump on below or equal/not above 0 1 1 1 0 1 1 0 disp jp/jpe = jump on parity/parity even 0 1 1 1 1 0 1 0 disp jo = jump on overflow 0 1 1 1 0 0 0 0 disp js = jump on sign 0 1 1 1 1 0 0 0 disp jne/jnz = jump on not equal/not zero 0 1 1 1 0 1 0 1 disp jnl/jge = jump on not less/greater or equal 0 1 1 1 1 1 0 1 disp jnle/jg = jump on not less or equal/greater 0 1 1 1 1 1 1 1 disp jnb/jae = jump on not below/above or equal 0 1 1 1 0 0 1 1 disp jnbe/ja = jump on not below or equal/above 0 1 1 1 0 1 1 1 disp jnp/jpo = jump on not par/par odd 0 1 1 1 1 0 1 1 disp jno = jump on not overflow 0 1 1 1 0 0 0 1 disp jns = jump on not sign 0 1 1 1 1 0 0 1 disp loop = loop cx times 1 1 1 0 0 0 1 0 disp loopz/loope = loop while zero/equal 1 1 1 0 0 0 0 1 disp loopnz/loopne = loop while not zero/equal 1 1 1 0 0 0 0 0 disp jcxz = jump on cx zero 1 1 1 0 0 0 1 1 disp int = interrupt type specified 1 1 0 0 1 1 0 1 type type 3 1 1 0 0 1 1 0 0 into = interrupt on overflow 1 1 0 0 1 1 1 0 iret = interrupt return 1 1 0 0 1 1 1 1 processor control clc = clear carry 1 1 1 1 1 0 0 0 cmc = complement carry 1 1 1 1 0 1 0 1 stc = set carry 1 1 1 1 1 0 0 1 cld = clear direction 1 1 1 1 1 1 0 0 std = set direction 1 1 1 1 1 1 0 1 cll = clear interrupt 1 1 1 1 1 0 1 0 st = set interrupt 1 1 1 1 1 0 1 1 hlt = halt 1 1 1 1 0 1 0 0 wait = wait 1 0 0 1 1 0 1 1 esc = escape (to external device) 1 1 0 1 1 x x x mod x x x r/m lock = bus lock prefix 1 1 1 1 0 0 0 0 instruction set summary (continued) mnemonic and description instruction code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 80c86
175 notes: al = 8-bit accumulator ax = 16-bit accumulator cx = count register ds= data segment es = extra segment above/below refers to unsigned value. greater = more positive; less = less positive (more negative) signed values if d = 1 then ?to? reg; if d = 0 then ?from? reg if w = 1 then word instruction; if w = 0 then byte instruction if mod = 11 then r/m is treated as a reg field if mod = 00 then disp = o ? , disp-low and disp-high are absent if mod = 01 then disp = disp-low sign-extended 16-bits, disp-high is absent if mod = 10 then disp = disp-high:disp-low if r/m = 000 then ea = (bx) + (si) + disp if r/m = 001 then ea = (bx) + (di) + disp if r/m = 010 then ea = (bp) + (si) + disp if r/m = 011 then ea = (bp) + (di) + disp if r/m = 100 then ea = (si) + disp if r/m = 101 then ea = (di) + disp if r/m = 110 then ea = (bp) + disp ? if r/m = 111 then ea = (bx) + disp disp follows 2nd byte of instruction (before data if required) ? except if mod = 00 and r/m = 110 then ea = disp-high: disp-low. ?? mov cs, reg/memory not allowed. if s:w = 01 then 16-bits of immediate data form the operand. if s:w. = 11 then an immediate data byte is sign extended to form the 16-bit operand. if v = 0 then ?count? = 1; if v = 1 then ?count? in (c l ) x = don't care z is used for string primitives for comparison with zf flag. segment override prefix 001 reg 11 0 reg is assigned according to the following table: 16-bit (w = 1) 8-bit (w = 0) segment 000 ax 000 al 00 es 001 cx 001 cl 01 cs 010 dx 010 dl 10 ss 011 bx 011 bl 11 ds 100 sp 100 ah 00 es 101 bp 101 ch 00 es 110 si 110 dh 00 es 111 di 111 bh 00 es instructions which reference the flag register file as a 16-bit object use the symbol flags to represent the file: flags = x:x:x:x:(of):(df):(i f):(tf):(sf):(zf):x:(af):x:(pf):x:(cf) mnemonics ? intel, 1978 instruction set summary (continued) mnemonic and description instruction code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
176 dual-in-line plastic packages (pdip) notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions, the inch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the ?mo series symbol list? in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are measured with the package seated in jedec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shal l not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be per- pendicular to datum . 7. e b and e c are measured at the lead tips with the leads uncon- strained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dam- bar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a1 -a- 0.010 (0.25) c a m bs e40.6 (jedec ms-011-ac issue b) 40 lead dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.250 - 6.35 4 a1 0.015 - 0.39 - 4 a2 0.125 0.195 3.18 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.030 0.070 0.77 1.77 8 c 0.008 0.015 0.204 0.381 - d 1.980 2.095 50.3 53.2 5 d1 0.005 - 0.13 - 5 e 0.600 0.625 15.24 15.87 6 e1 0.485 0.580 12.32 14.73 5 e 0.100 bsc 2.54 bsc - e a 0.600 bsc 15.24 bsc 6 e b - 0.700 - 17.78 7 l 0.115 0.200 2.93 5.08 4 n40 409 rev. 0 12/93 80c86
177 ceramic dual-in-line fr it seal packages (cerdip) notes: 1. index area: a notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. 2. the maximum limits of lead di mensions b and c or m shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. 4. corner leads (1, n, n/2, and n/2+1) may be configured with a partial lead paddle. for this co nfiguration dimension b3 replaces dimension b2. 5. this dimension allows for off- center lid, meniscus, and glass overrun. 6. dimension q shall be measured from the seating plane to the base plane. 7. measure dimension s1 at all four corners. 8. n is the maximum number of terminal positions. 9. dimensioning and tolerancing per ansi y14.5m - 1982. 10. controlling dimension: inch. bbb c a - b s c q l a seating base d plane plane -d- -a- -c- -b- d e s1 b2 b a e m c1 b1 (c) (b) section a-a base lead finish metal e a/2 a m s s ccc c a - b m d s s aaa ca - b m d s s e a f40.6 mil-std-1835 gdip1-t40 (d-5, configuration a) 40 lead ceramic dual-in-line frit seal package symbol inches millimeters notes min max min max a - 0.225 - 5.72 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 d - 2.096 - 53.24 5 e 0.510 0.620 12.95 15.75 5 e 0.100 bsc 2.54 bsc - ea 0.600 bsc 15.24 bsc - ea/2 0.300 bsc 7.62 bsc - l 0.125 0.200 3.18 5.08 - q 0.015 0.070 0.38 1.78 6 s1 0.005 - 0.13 - 7 90 o 105 o 90 o 105 o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - m - 0.0015 - 0.038 2, 3 n40 408 rev. 0 4/94 80c86

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